1. Field of the Invention
The present invention relates generally to a field effect transistor switch circuit and, in particular, to a field effect transistor switch circuit for high frequency and high power applications.
2. Related Art of the Invention
Switches composed of MES field effect transistors are widely used in high frequency and high power applications. In these switches, signal lines are switched using the ON and OFF resistances of the transistors.
In general, MES field effect transistors are of depletion type. That is, their threshold voltage Vth below which the drain current becomes zero is negative. Accordingly, when the gate-source potential difference Vgs is 0 V, such a field effect transistor is ON. In order for the field effect transistor to go OFF, a voltage below the threshold voltage Vth needs to be applied. In prior art apparatuses, this voltage has generally been obtained from a negative power supply. However, in another prior art apparatus, internal self-bias effect of a field effect transistor is utilized to generate a reference bias voltage, whereby the necessity of an external bias circuit is avoided (Japanese Laid-Open Patent Publication No. H9-181588).
A DPDT (double pole double throw) switch which needs no external bias circuit is described below in detail as an example of a prior art field effect transistor switch circuit.
FIG. 5 is a circuit diagram showing a DPDT switch which needs no external bias circuit. The DPDT switch comprises four switch terminals, which are two switch input terminals 1 and 3 and two switch output terminals 2 and 4. The switch input terminals 1 and 3 receive input signals IN1 and IN2, respectively. The switch output terminals 2 and 4 provide output signals OUT1 and OUT2, respectively.
Four sets of field effect transistors 5a–5d, 6a–6d, 7a–7d, 8a–8d are arranged respectively between the switch input terminals 1 and 3 and the switch output terminals 2 and 4. Voltages of +Vc and 0 V are selectively applied as control voltages Vc1 and Vc2 to the control terminals 21 and 22, whereby the gate voltages of the field effect transistors 5a–5d, 6a–6d, 7a–7d, 8a–8d are controlled. As a result, the field effect transistors 5a–5d, 6a–6d, 7a–7d, 8a–8d go ON and OFF, and thereby switch the signal lines. In this example, the sources of the field effect transistors 5a–5d, 6a–6d, 7a–7d, 8a–8d are oriented toward the switch input terminal 1 or 3, while the drains are oriented toward the switch output terminal 2 or 4.
Two signal path configurations are available in this apparatus. In a first path configuration, the input signal IN1 inputted to the switch input terminal 1 is outputted as the output signal OUT1 from the switch output terminal 2, while the input signal IN2 inputted to the switch input terminal 3 is outputted as the output signal OUT2 from the switch output terminal 4.
In a second path configuration, the input signal IN1 inputted to the switch input terminal 1 is outputted as the output signal OUT2 from the switch output terminal 4, while the input signal IN2 inputted to the switch input terminal 3 is outputted as the output signal OUT1 from the switch output terminal 2.
Resistors 9a–9d, 10a–10d, 11a–11d, 12a–12d are connected respectively between the gates of the field effect transistors 5a–5d, 6a–6d, 7a–7d, 8a–8d and the control terminal 21 or 22.
DC cut capacitors 13, 14, 15, 16 are connected respectively between: the field effect transistors 5a, 5d, 6a, 6d, 7a, 7d, 8a, 8d; and the switch input terminals 1 and 3 and the switch output terminals 2 and 4.
In FIG. 5, when voltages of +Vc and 0 V are applied respectively as the control voltages Vc1 and Vc2 to the control terminals 21 and 22, relations between potentials at various points connected to the control terminal 21 or 22 become as described below.
When the potentials at the control terminals 21 and 22 are denoted by V(Vc1) and V(Vc2), respectively, the voltage condition is expressed as follows.+Vc=V(Vc1)0V=V(Vc2)The gate potential V(G8d) of the field effect transistor 8d is lower than the potential V(Vc1) of the control terminal 21 because of the voltage drop across the resistor 12d. 
In the field effect transistor 8d, a forward current flows through the P-N junction from the gate G8d to the source S8d, thereby generates a voltage drop. In the field effect transistor 5a, a reverse current flows through the P-N junction from the source S5a to the gate G5a, thereby generates a voltage drop.
Further, a resistor 9a generates a voltage drop between the gate G5a of the field effect transistor 5a and the control terminal 22.
These relations are summarized by the following single expression.+Vc=V(Vc1)>V(G8d)>V(S8d)=V(S5a)>V(G5a)>V(Vc2)=0VHere, symbol V(S8d) denotes the source potential of the field effect transistor 8d. Symbol V(S5a) denotes the source potential of the field effect transistor 5a. Symbol V(G5a) denotes the gate potential of the field effect transistor 5a. 
In such a bias condition, in the field effect transistor 8d, a forward current flows through the P-N junction because of the forward bias. In the field effect transistor 5a, a reverse current flows through the P-N junction because of the reverse bias.
However, a DC cut capacitor 13 is connected to the switch input terminal 1. Accordingly, the forward current equals the reverse current. Further, if a forward bias and a reverse bias having the same voltage are applied to P-N junctions, the forward current is substantially larger than the reverse current. Accordingly, when the same current flows through the P-N junctions, the voltage drop is substantially larger in the reverse bias than in the forward bias. That is,V(G8d)−V(S8d)<<V(S5a)−V(G5a)Thus, usingV(S5a)=V(S8d)the following relation is obtainedV(S5a)≈V(G8d)
Since the currents flowing through the P-N junctions are sufficiently small, the voltage drops in the resistors 9a and 12d are negligibly small. Thus,V(G8d)≈Vc and V(G5a)≈0VAccordingly,V(S5a)≈Vc
As a result, the field effect transistor 5a goes OFF, while the field effect transistor 8d goes ON.
Similarly, the field effect transistors 5b–5d and 7a–7d goes OFF, while the field effect transistors 6a–6d and 8a–8c goes ON.
As such, only the control voltages Vc1 and Vc2 cause the field effect transistors 5a–5d, 6a–6d, 7a–7d, 8a–8d to serve as switching elements.
Numeral D5a indicates the drain of the field effect transistor 5a. Numerals D5d, S5d, and G5d indicate respectively the drain, source, and gate of the field effect transistor 5d. Numerals D6a, S6a, and G6a indicate respectively the drain, source, and gate of the field effect transistor 6a. Numerals D6d, S6d, and G6d indicate respectively the drain, source, and gate of the field effect transistor 6d. Numerals D7a, S7a, and G7a indicate respectively the drain, source, and gate of the field effect transistor 7a. Numerals D7d, S7d, and G7d indicate respectively the drain, source, and gate of the field effect transistor 7d. Numerals D8a, S8a, and G8a indicate respectively the drain, source, and gate of the field effect transistor 8a. Numeral D8d indicates the drain of the field effect transistor 8d. 
A technical problem in the prior art is that the depletion layer expands due to electron trapping effect, whereby the DC potentials of the switch input terminals 1 and 3 exceed +Vc+Vth. In case that the DC potentials of the switch input terminals 1 and 3 rise to this level, the field effect transistors do not go ON even when the gate potentials are set at the voltage +Vc.
The problem that the DC potentials of the switch input terminals 1 and 3 rise to this level is described below in detail. In the field effect transistor switch circuit shown in FIG. 5, all the field effect transistors 5a–5d, 6a–6d, 7a–7d, 8a–8d have the same characteristics. Further, the gate-source capacitance equals the gate-drain capacitance in each field effect transistor 5a–5d, 6a–6d, 7a–7d, 8a–8d. The gate of each field effect transistor 5a–5d, 6a–6d, 7a–7d, 8a–8d is biased through a resistor 9a–9d, 10a–10d, 11a–11d, 12a–12d having a high resistance. Thus, the bias circuit equivalently has a high impedance for high frequency.
When voltages of +Vc and 0 V are applied respectively as the control voltages Vc1 and Vc2 to the control terminals 21 and 22, the field effect transistors 5a–5d shown in FIG. 5 go OFF. These field effect transistors 5a–5d in the OFF state are equivalent to a serial connection of eight capacitances composed of the gate-source capacitances C and the gate-drain capacitances C. FIG. 6 schematically shows these capacitances C and the gate resistors 9a–9d. 
When a high frequency signal having an amplitude of Vin is inputted as the input signal IN1 to the switch input terminal 1, the high frequency signal is divided by the gate-source capacitances C and the gate-drain capacitances C of the field effect transistors 5a–5d. As a result, the time-dependent changes in the potentials V(S5a), V(G5a), and V(D5a) of the source S5a, the gate G5a, and the drain D5a of the field effect transistor 5a are as shown in FIG. 7. The vertical axis in FIG. 7 indicates the potential at each measurement point, while the horizontal axis indicates the time.
In the field effect transistor 5a, the bias conditions at t=t1 and at t=t2 are as shown in FIGS. 8A and 8B, respectively. When the amplitude of the input signal is large, the field effect transistor 5a goes under a strong reverse bias condition at t=t1 and t=t2.
FIGS. 9A and 9B are cross sectional views of the structure of the field effect transistor 5a which is the first-stage field effect transistor relative to the switch input terminal 1 among the field effect transistors 5a–5d in the OFF state. In FIGS. 9A and 9B, mark “+” indicates a hole, while encircled mark “−” indicates an electron.
As shown in FIG. 9A, when a voltage of 0 V is applied to the gate, the depletion layer under the gate extends to the channel, whereby the field effect transistor 5a go OFF. However, when a signal having a large amplitude is applied to the source terminal and when the P-N junction thereby goes under a reverse bias condition as described above, a leak current flows from the gate, whereby electrons are trapped in the surface potentials (traps) between the gate and the source and between the gate and the drain. The depletion layer expands proportionally to the number of electrons. FIG. 9B illustrates the expanded depletion layer. The field effect transistor 5a immediately adjacent to the switch input terminal receives a signal having the largest amplitude. This causes a large reverse bias, and hence a wide expansion in the depletion layer.
Even when the depletion layer is in the expanded state, the field effect transistors 5a–5d are OFF. Accordingly, the field effect transistors 5a–5d are equivalent to a serial connection of eight capacitances composed of the gate-source capacitances and the gate-drain capacitances.
However, since the depletion layer is in the expanded state as described above, the gate-source capacitance of the field effect transistor 5a is smaller than the other gate-source capacitances and the gate-drain capacitances. The capacitance of each portion with an unexpanded depletion layer is C, while the capacitance of the portion with an expanded depletion layer is assumed to (½)C for simplicity. FIG. 10 schematically shows these capacitances and the resistors 9a–9d. 
In such a situation, when a high frequency signal having an amplitude of Vin is inputted as the input signal IN1 to the switch input terminal 1, the time-dependent changes in the potentials V(S5a), V(G5a), and V(D5a) of the source S5a, the gate G5a, and the drain D5a of the field effect transistor 5a are as shown in FIG. 11. In this case, the gate-source capacitance of the field effect transistor 5a equals ½ of each of the gate-drain capacitances and the gate-source capacitances of the other field effect transistors 5b–5d. Accordingly, in contrast to FIG. 7, the voltage drop of the capacitance between the source S5a and the gate G5a of the field effect transistor 5a is twice value of each of the other capacitances.
The potentials of the source S5a, the gate G5a, and the drain D5a of the field effect transistor 5a at t=t1 and t2 behave as follows. As shown in FIG. 12, when the amplitude of the input signal is small, the field effect transistor 5a remains OFF. In contrast, when the amplitude of the input signal is large, the field effect transistor 5a goes ON. When the field effect transistor 5a goes ON, electric charge moves from the DC cut capacitor 14 to the DC cut capacitor 13. As a result, the DC cut capacitor 13 is charged up, and hence the DC potential of the switch input terminal 1 rises.
The potential of the switch input terminal 1 is at approximately Vc in the original state. Accordingly, when the potential rises slightly, the potential exceeds Vc immediately. Even when the state V(S5a)−Vc>Vth is reached, the field effect transistors 8a–8d do not go ON in case that Vc1=+Vc.
Accordingly, in this prior art field effect transistor switch circuit, when a signal having a large amplitude is inputted, the depletion layer expands due to electron trapping effect, whereby unbalance occurs between the DC cut capacitors 13 and 14. This causes a rise in the DC potential of the switch input terminal 1, and thereby disables ON/OFF switching operations which are the basic operations of a switch.
As such, the gate-source capacitance of the field effect transistor in the OFF state decreases due to the expansion of the depletion layer, whereas the gate-drain capacitance does not decrease regardless of the expansion of the depletion layer. This fact is described below. In FIG. 5, it is assumed that the field effect transistors 8a–8d are OFF and that the field effect transistors 5a–5d are ON. In this case, the field effect transistors 8a–8d are approximated as a serial connection circuit of capacitances. Assuming that the depletion layers are normal, the potentials V(S8d), V(G8d), V(D8d) are as shown in FIG. 13. At t=t2, the gate-drain voltage isVgd=3−(⅛)Vawhile the gate-source voltage isVgs=3+(⅛)VaThat is, Vgs>Vgd. This indicates that the depletion layer expands more in the gate-source region than in the gate-drain region.